Synthesis

• FOSSY stand for Functional Oldenburg System SYnthesiser
• FOSSY is a tool for transforming system-level SystemC models to synthesisable VHDL.
• FOSSY enables a seamless design flow for embedded HW/SW systems using the OSSS Methodology.

FOSSY and the OSSS Methodology are developed at the OFFIS Institute for Information Technology, an application oriented research and development institute working on system-level design methodologies for more than ten years. Two consecutive research projects (funded by the European Union) in cooperation with leading industrial partners resulted in robust tools with a focus on practical applicability. FOSSY and the OSSS Methodology will be commercially available in 2009.

A more detailed overview of Fossy's features is available, here.

The Fossy user manual can be downloaded here.

We start with a C++ “Golden Model” as a base for further refinements. In the first step the model is broken into structural blocks. The different structural blocks are represented by SystemC modules and OSSS Shared Objects. OSSS Shared Objects model communication and synchronisation between parallel processes with a method based interface. Shared Objects can contain any user class and guarantee consistent access from any number of client processes.

This first structural description is called Application Layer Model. In this models we can use powerful features from C++, SystemC and OSSS:

• Object orientation for encapsulating data and methods in classes and objects
• Templates for generic programming
• SystemC modules for modelling parallelism
• Method based communication with Shared Objects
• OSSS Software Tasks for components implemented in software

The Application Layer Model contains the functionality, the logical structure and a first approximation of the timing behaviour of the system (profiling data from the software analysis can be annotated into the model).

The executable Application Layer Model is used to verify the correctness of the model and to explore implementations with different HW/SW partitionings and/or different communication structures.

The next step is the refinement to a Virtual Target Architecture Model. Implementation details like bus protocols, bitwidths of communication channels and processor types are added to the model. By specifying these details the model is now cycle-accurate.

Application Layer Model and Virtual Target Architecture Model are input for the FOSSY synthesis tool. FOSSY generates efficient synthesisable VHDL for the hardware parts and the communication structures as well as C++ code for the software and the bus drivers.

The output of FOSSY is combined with platform-specific configuration files and code extracted directly from the Virtual Target Architecture Model. Industrial standard 3rd party tools (e.g. the Xilinx XST) take the configuration, VHDL and C++ code and generate the bitstream for the implementation in a platform FPGA.