@inproceedings{ittershagen_mc_modelling_2015,
	author = {Philipp Ittershagen and and Kim Gr{\"u}ttner and Wolfgang Nebel},
	title = "Mixed-Criticality System Modelling with Dynamic Execution Mode Switching",
	year = 2015,
	month = sep,
	booktitle = "Proceedings of the Forum on Specification and Design Languages (FDL'2015)",
	url = "http://ecsi.org/fdl",
	abstract = "In this paper, an executable system model for performing a functional simulation while observing the dynamic effects of mixed-criticality requirements regarding applications with different levels of assurance is proposed. The model provides the expression of dynamic execution modes and execution time estimates on each criticality level of the system. In a refinement step, it is possible to observe the effects of scheduling policies, dynamic criticality-, and execution mode switches on the functional behaviour of the system in a trace-based, simulative manner. An early evaluation of a quadrocopter platform consisting of a safety critical flight control application and a video-based, performance critical object detection is used to demonstrate the applicability of the design flow. Simulation results indicate that by defining multiple execution modes of the object detection algorithm, the run-time utilisation feedback allows the algorithm to run in a high-quality mode for more than 50% of the time, thereby increasing the overall system utilisation by two thirds compared to a static resource utilisation analysis."
}

@inproceedings{ittershagen_sw_performance_2015,
	author = {Philipp Ittershagen and Philipp A. Hartmann and Kim Gr{\"u}ttner and Wolfgang Nebel},
	title = "A Workload Extraction Framework for Software Performance Model Generation",
	year = 2015,
	month = jan,
	abstract = "The early performance evaluation of complex platforms and software stacks requires fast and sufficiently accurate workload representations. In the literature, two different approaches have been proposed: Host--based simulation with abstract performance annotations, enabling fast and functional simulations with limited architectural accuracy, and abstract workload models (or traffic generators) with more detailed platform resource usage patterns. In this work, we present an approach for automatic workload extraction from functional application code, combining the benefits of both approaches. First, the algorithmic behaviour of the embedded software is characterised statically both in terms of target processor usage and target memory access patterns, resulting in an abstracted, control flow--aware workload model. Secondly, this model can be used on the target architecture itself as well as within a host--based simulation environment. We demonstrate the effectiveness of our approach by running our performance model on a virtual platform with and without a target Instruction Set Simulator (ISS) and comparing the simulation traces with the unaltered target processor binary execution.",
	booktitle = "7th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO'15)",
	url = "http://www.rapido.deib.polimi.it/"
}

@inproceedings{sschreiner:2015:mbmvm,
	author = {Schreiner, S{\"o}ren and Gr{\"u}ttner, Kim and Rosinger, Sven and Nebel, Wolfgang},
	title = "Ein Verfahren zur Bestimmung eines Powermodells von Xilinx MicroBlaze MPSoCs zur Verwendung in Virtuellen Plattformen",
	year = 2015,
	month = mar,
	abstract = "Durch die Einführung von Multi-Processor-System-on-Chips werden die steigenden Anforderungen an die Performanz für moderne Eingebettete Systeme erfüllt. Oft sind diese aber im mobilen Einsatz und müssen insbesondere Anforderungen an ihre Leistungsaufnahme erfüllen. Die vorliegende Arbeit stellt einen Ansatz vor, wie durch Charakterisierung einer realen Hardware eine Virtuelle Plattform des gleichen Systems mit gemessenen Verlustleistungsdaten annotiert werden kann. So können echte Anwendungen auf der Virtuellen Plattform ausgeführt und Vorhersagen über die Leistungsaufnahme des realen Systems getätigt werden. Zur ersten Evaluation des beschriebenen Ansatzes wurde ein Xilinx MicroBlaze MPSoC Designs auf einem FPGA implementiert, mit Hilfe von Micro-Benchmarks dessen Verlustleistung charakterisiert und daraus ein Power State Machine Modell erstellt. Dieses wurde in einer OVP-basierten Virtuellen Plattform des gleichen Designs integriert und dessen Verlustleistungsvorhersage in einer Co-Simulation mit der Messung der Verlustleistung am FPGA-Design verglichen. Für die durchgeführten Experimente hat sich ein akkumulierter Fehler kleiner als 1% ergeben.",
	booktitle = "18. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015)"
}

@inproceedings{Lorenz:2014:TPSMM,
	title = "Trace-Based Power State Machine Modelling",
	author = {Lorenz, Daniel and Gr\"{u}ttner, Kim and Ortland, Vincent},
	booktitle = "Proceedings of the Forum on specification and Design Languages (FDL'2014)",
	year = 2014,
	abstract = "Due to the increasing algorithmic complexity of todays embedded systems, the consideration of extra-functional properties becomes even more important. Extra-functional properties such as timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gate-level, several techniques are available, but there is still a lack of methods and tools for power estimation and analysis at electronic system level (ESL) and above. In todays systems most of the hardware is not design from scratch, but bought as black-box components from IP vendors. Our Power State Machine (PSM) model enables power simulation of these components at ESL by deriving the power of communication at the component’s interfaces. In this work we present an Eclipse plug-in which supports the designer or user of a black-box IP component in creating the PSM model based on gate-level simulations and power estimations."
}

@inproceedings{Lorenz:2014:DSPCSBRICSL,
	title = "Data- and State-Dependent Power Characterisation and Simulation of Black-Box {RTL IP} Components at System Level",
	author = {Daniel Lorenz and Kim Gr\"{u}ttner and Wolfgang Nebel},
	booktitle = "17th Euromicro Conference on Digital Systems Design (DSD 2014)",
	year = 2014,
	abstract = "Due to the increasing algorithmic complexity of todays embedded systems, the consideration of extra-functional properties becomes even more important. Extra-functional properties such as timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gate-level, several techniques are available, but there is still a lack of methods and tools for power estimation and analyses at electronic system level (ESL) and above. Existing ESL methods in most cases use state-based methods for power simulation. This may lead to inaccurate results, especially for data-dependent designs. In this paper, we extend the Power State Machine (PSM) model for black-box RTL IP components with a mechanism that employs data-dependent switching activity using the Hamming distance (HD). In pipelined designs, we do not only consider the input HD but also the HDs of the internal pipeline stage registers. Since these registers of black-box IP are not observable from the outside, our model derives the internal HDs from previous input data. The results show that our extension achieves up to 38% better results than the previous PSM approach and up to 35% better results compared to a model considering only the input HD."
}

@inproceedings{jwalter_raspi_rtsim_2014,
	author = {Walter, J{\"o}rg and Fakih, Maher and Gr{\"u}ttner, Kim},
	title = "Hardware--Based Real--Time Simulation on the Raspberry Pi",
	year = 2014,
	month = jan,
	booktitle = "2nd Workshop on High-performance and Real-time Embedded Systems (HiRES 2014)",
	abstract = "Hardware prototypes are commonly used during embedded control unit design. Existing commercial tools offer an integrated workflow from mathematical models down to hardware simulation. Researchers also build low-cost simulation platforms out of commodity equipment. We present a platform that is an order of magnitude cheaper than existing systems but still easy to integrate into present workflows: Within an existing model-driven design methodology, we perform real-time hardware simulation using the Raspberry Pi single-board computer to simulate an electromechanical system with little development effort."
}

@inproceedings{Sauppe:2013:DIPDSL,
	author = {Matthias Sauppe and Thomas Horn and Erik Markert and Ulrich Heinkel and Daniel Lorenz and Kim Gr{\"u}ttner and Hans-Werner Sahm and Klaus-Holger Otto},
	title = "A Database for the Integration of Power Data on System Level",
	year = 2013,
	month = jul,
	abstract = "Using state of the art design methods, advanced calculation of system power budgets is a major challenge. Currently, system design methods do not offer sufficient means for supporting energy awareness and efficiency throughout the complete system design process. In this paper, we present a power database for storing and predicting power data of integrated systems across abstraction levels, starting at system level and going all the way down to gate level. Our approach bases on the definition of multiple use cases per component, which allows for accurate power prediction of hierarchically defined systems al-ready during the system-level design stage. This leads to reduced design costs as early power-affecting design decisions can be made on a sound basis. For evaluation, use cases for a commercially used network router component and its subcomponents were generated and power-simulated. After applying the results to the power database, we show that use case based power prediction on system level can be highly accurate, as our example calculation results in an error of less than five percent.",
	organization = {IEEE" project = "enersave}
}

@inproceedings{Ittershagen:2013:HRTSMCEO,
	author = {Philipp Ittershagen and Philipp A. Hartmann and Kim Gr{\"u}ttner and Achim Rettberg},
	title = "Hierarchical Real-Time Scheduling in the Multi-Core Era - An Overview",
	booktitle = "IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)",
	year = 2013,
	month = jun,
	pages = "1-10",
	doi = "10.1109/ISORC.2013.6913241",
	abstract = {With the accelerating pervasiveness of multi-core platforms in the embedded domains and the on-going need for more computational power and increased integration, multi-core scheduling for real-time and mixed-critical applications is an active research topic. In this paper, we give an overview on the history and the current state-of-the-art on multi-core real-time scheduling. A special focus is put on shared resource access protocols and hierarchical scheduling approaches, both of which are increasingly important due to the higher spatial integration and stronger coupling between the different subsystems, both on the application and on the multi-core architectural level. Moreover, hierarchical scheduling is a promising approach in the area of mixed-criticality systems to enable composability and segregation, which is needed to cope with the complexity of such systems. This survey will be of interest to researchers and practitioners in the field of real-time scheduling for multi-core systems." project = "aramis}
}

@inproceedings{Fakih:2013:TPASMSBAUMC,
	author = {Fakih Maher and Kim Gr{\"u}ttner and Martin Fr{\"a}nzle and Achim Rettberg},
	title = "Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking",
	year = 2013,
	month = mar,
	abstract = "The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model- checking based approach will be described which allows us to guarantee timing bounds of multiple Synchronous Data Flow Graphs (SDFG) running on shared-bus multicore architectures. Our approach utilizes Timed Automata (TA) as a common semantic model to represent software components (SDF actors) and hardware components of the multicore platform. These TA are explored using the UPPAAL model-checker for providing the timing guarantees. Our approach shows a significant precision improvement compared with the worst-case bounds estimated based on maximal delay for every bus access. Furthermore, scalability is examined to demonstrate analysis feasibility for small parallel systems.",
	publisher = "European Design and Automation Association",
	series = "DATE '13",
	address = "3001 Leuven, Belgium, Belgium",
	booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2013" project = "motorbrain}
}

@inproceedings{Ittershagen:2013:ABKMPS,
	author = {Philipp Ittershagen and Philipp A. Hartmann and Kim Gr{\"u}ttner and Wolfgang Nebel},
	title = "Ansatz zur Bewertung der HW/SW-Kommunikation in asymmetrischen Multi-Prozessor-Systemen",
	year = 2013,
	pages = "197--208",
	month = mar,
	abstract = {Heutige Multi-Prozessor-Systeme verf{\"u}gen {\"u}ber komplexe Kommunikations- und Speicherhierarchien zur Synchronisation und zum Nachrichtenaustausch. Hinzu kommt eine Vielzahl von anwendungsspezifischen Hardwarekomponenten, die von unterschiedlichen Prozessoren gemeinsam genutzt werden k{\"o}nnen. Um die Hardwarekomplexit{\"a}t vor dem Anwender mit Hilfe eines geeigneten Programmiermodells zu verbergen, wird auch die Software-Architektur zunehmend m{\"a}chtiger. Zur Analyse der funktionalen und extra-funktionalen Einfl{\"u}sse der Software-Architektur und Konfiguration im Zusammenspiel mit der Hardwareplattform werden fortgeschrittene Analysemethoden und werkzeuge ben{\"o}tigt. Zu diesem Zweck wird im Rahmen dieser Arbeit ein flexibles Analysemodell, basierend auf einem parallelen Programmiermodell, vorgestellt. Das vorgeschlagene Modell, in Kombination mit einer virtuellen Hardwareplattform des Zielsystems, ist in der Lage das Zeitverhalten unterschiedlicher Workloadmodelle unter Ber{\"u}cksichtigung von RTOS-, Treiber- und Kommunikationsartefakten zu charakterisieren. Zur Evaluation wird ein Linux-basiertes Betriebssystem auf einer ARM Dual-Core Plattform mit einer von beiden Prozessoren genutzten Hardware-Ressource bzgl. des Antwortzeitverhaltens unter verschiedenen Workload-, Betriebssystem- und Plattformparametern untersucht.},
	booktitle = "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2013)",
	organization = {Universit{\"a}t Rostock}
}

@misc{Gruettner:2013:PEMACVP,
	author = {Kim Gr{\"u}ttner and Philipp A. Hartmann and Frank Oppenheimer},
	title = "Performance and Energy Modeling and Analysis in COMPLEX Virtual Platform",
	year = 2013,
	month = 02" project = "complex
}

@techreport{seamless_seg2013,
	author = {Reinkemeier, Philipp and Ittershagen, Philipp and Stierand, Ingo and Hartmann, Philipp A. and Henkler, Stefan and Gr{\"u}ttner, Kim},
	title = "{Seamless} {Segregation} for {Multi-Core} {Systems}",
	year = 2013,
	month = ,
	institution = "OFFIS"
}

@inproceedings{Lorenz:2012:RIFSMEP,
	title = "From {RTL} {IP} to Functional System--Level Models with Extra--Functional Properties",
	booktitle = "CODES+ISSS’12",
	author = {Daniel Lorenz and Kim Gr{\"u}ttner and Nicola Bombieri and Valerio Guarnieri and Sara Bocchio},
	month = oct,
	year = 2012,
	location = "Tampere, Finland",
	abstract = "The paper presents a novel abstraction methodology for generating time-- and power--annotated TLM models from synthesizable RTL descriptions. The proposed techniques allow the integration of existing RTL IP components into virtual platforms for early software development and platform design, configuration, and exploration. With the proposed approach, IP models can be natively integrated into SystemC TLM--2.0 platforms and executed 10--1000 times faster compared to state--of--the--art RTL simulators. The abstraction methodology guarantees preservation of the behaviour and timing of the RTL models. Target technology dependent power properties of IP components are represented as power state--machines and integrated into the abstracted TLM models. The experimental results show a relative error less than 10{\%} of the abstracted model's power consumption compared to state--of--the--art RTL power simulators. The evaluation has been performed on RTL IP components with different characteristics and demonstrates the effectiveness of the presented abstraction methodology."
}

@inproceedings{Gruettner:2012:CCMPE,
	author = {Kim Gr{\"u}ttner and Philipp A. Hartmann and Kai Hylla and Sven Rosinger and Wolfgang Nebel and Fernando Herrera and Eugenio Villar and Carlo Brandolese and William Fornaciari and Gianluca Palermo and Chantal Ykman-Couvreur and Davide Quaglia and Francisco Ferrero and Raul Valencia},
	title = "COMPLEX -- COdesign and power Management in Platform--based design space EXploration",
	year = 2012,
	month = sep,
	abstract = "The consideration of an embedded devices power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of todays heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a design flow concept that combines system--level power optimization techniques with platform--based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives and power management strategies. Our proposed flow combines system--level timing and power estimation techniques available in commercial tools with platformbased rapid prototyping. We propose an efficient code annotation technique for timing and power properties that enables fast host execution as well as adaptive collection of power traces. Combined with a flexible design--space exploration (DSE) approach our flow allows a trade--off between different platforms, mapping alternatives, and optimization techniques, based on domainspecific workload scenarios. The proposed flow is currently under implementation in the COMPLEX FP7 European integrated project.",
	organization = "Euromicro",
	booktitle = "15th Euromicro Conference on Digital System Design (DSD)"
}

@inproceedings{Lorenz:2012:NPSSS,
	author = {Daniel Lorenz and Philipp A. Hartmann and Kim Gr{\"u}ttner and Wolfgang Nebel},
	title = "Non--invasive Power Simulation at System--Level with SystemC",
	year = 2012,
	month = sep,
	abstract = "Due to the increasing algorithmic complexity of today's embedded systems, consideration of extra--functional properties becomes more important. Extra--functional properties like timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT-- and gate--level several techniques are available, but there is still a lack of methods and tools for power estimation and analyses at system and higher levels. In this paper we present an approach for non--invasive augmentation of functional SystemC(TM) TLM--2.0 components with power properties. The I/O behaviour of a TLM--2.0 component will be observed by a Protocol State Machine (PrSM) that generates trigger events to stimulate a Power State Machines (PSM). The PSM describes the component's internal power states and transitions and transitions between them. Each component's PSM is connected with a frequency and voltage dependent power model. We present first evaluation results of different IP components and compare our system--level power traces generation with state--of--the--art gate--level power simulations in terms of accuracy and simulation speed.",
	booktitle = "International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2012"
}

@inproceedings{Gruettner:2012:TPEEESDVP,
	author = {Kim Gr{\"u}ttner and Philipp A. Hartmann and Tiemo Fandrey and Kai Hylla and Domenik Helms and Frank Oppenheimer and Wolfgang Nebel and Achim Rettberg},
	title = "Towards Performance and Energy Efficient Embedded System Design using Virtual Platforms",
	year = 2012,
	month = jun,
	booktitle = "The 2012 Electronic System Level Synthesis Conference (ESLsyn)"
}

@inproceedings{Nebel:2012:UNMS,
	author = {Wolfgang Nebel and Domenik Helms and Kim Gr{\"u}ttner and Frank Oppenheimer},
	title = {{\"U}ber die Notwendigkeit neuer Modellierungskonzepte komplexer eingebetteter Systeme},
	year = 2012,
	month = may,
	abstract = {Eingebettete Systeme waren stets komplex, ihr Entwurf immer aufw{\"a}ndig, risikoreich und kostspielig. Gleichwohl sind und bleiben sie DIE Innovationstreiber. Die Herausforderungen ihres Entwurfs konnten in der Vergangenheit durch gewaltige Fortschritte der Entwurfsverfahren beherrscht werden. Aber keine Industrie wird vergleichbar der Mikroelektronik st{\"a}ndig vor neue Herausforderungen gestellt der Preis der enormen Innovationsleistung: Mit jeder L{\"o}sung eines Entwurfsproblems wird eine Innovationswelle ausgel{\"o}st -- und neue Herausforderungen. EDA--Forschung eine Sisyphusarbeit? Nein, die Ziele werden erreicht, man erklimmt den Berg, aber dahinter liegt ein neuer Gipfel mit neuen wirtschaftlichen Chancen, aber auch neuen Forschungsaufgaben. Eine der derzeitigen Aufgaben liegt darin, Systeme zu entwickeln und zu optimieren, die eine zunehmende Menge von Randbedingungen erf{\"u}llen und Eigenschaften aufweisen m{\"u}ssen. Sie sollen gleichzeitig leistungsf{\"a}hig sein, kosteng{\"u}nstig, energieeffizient, echtzeitf{\"a}hig, robust und zuverl{\"a}ssig. Sie sollen f{\"u}r unterschiedliche Aufgaben optimiert sein, trotzdem flexibel und konform zu Standards. Sie sollen auch im Entwurf kosteng{\"u}nstig sein und in ihren Eigenschaften vorhersehbar. Dies f{\"u}hrt zu heterogenen Systemen mit unterschiedlichen Prozessorkernen, analogen Komponenten, anwendungsspezifischen Coprozessoren und Standardmodulen. Zus{\"a}tzlich erschweren Alterungseffekte neuer Halbleitertechno--logien, enge thermische Grenzen, neue Packaging--Konzepte den Entwurf. Ein verl{\"a}sslicher Entwurf und eine zielorientierte Optimierung solcher komplexer Systeme erfordern eine sehr fr{\"u}hzeitige quantitative Bewertung der Vielzahl der Qualit{\"a}tseigenschaften dieser Systeme. Hierf{\"u}r ist ein Modellierungskonzept bestehend aus abstrakten, verl{\"a}sslichen und interoperablen Modellen heterogener Systemkomponenten notwendig.},
	organization = "edacentrum",
	booktitle = {edaWorkshop 2012" Project = "none}
}

@inproceedings{Poppen:2012:CCSSMS,
	author = {Frank Poppen and Kim Gr{\"u}ttner},
	title = "Co--Simulation of C--based SoC Simulators and MATLAB Simulink",
	year = 2012,
	month = mar,
	abstract = "Simulation of systems under development is a widely used methodology for early design evaluation and performance analysis. Many engineers trust on MATLAB {\&}amp; Simulink as a simulation environment, especially since it offers many domain specific block sets for fast, easy and efficient use. With its ability to generate life source code from the simulation model it becomes a powerful development tool. After code generation it is common practice to proceed to the real world and maybe coupling HW executing the generated SW with simulation (HW in the loop simulation), which can be considered to be a big jump into the cold water. The contribution of this paper is a concept and proof--of--concept implementation of a co--simulation interface between a C--based System on Chip (SoC) model and MATLAB {\&}amp; Simulink. The proposed approach enables the coupling of application domain specific high level simulation with a bit and cycle accurate virtual execution platform of a specific embedded HW/SW platform without interfacing troubles. Our concept was implemented for and applied to the development of an embedded medical device a Wearable Artificial Kidney Device (WAKD).",
	organization = "Operational Research Society",
	booktitle = "Simulation Workshop 2012 (SW12)"
}

@proceedings{Leupers:2012:DFWQVVPCSTT,
	title = "DATE 2012 Friday Workshop (W2): Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow",
	author = {Rainer Leupers and Christian Haubelt and Achim Rettberg and Kim Gr{\"u}ttner},
	month = mar,
	year = 2012,
	abstract = "Nowadays, the deployment of Virtual Platform models is an industry--proven technique in a wide variety of design tasks from pre--silicon software development to performance analysis and exploration. With the increasing complexity, both in terms of the applications and the target platforms (e.g. increasing number of cores, more complex memory hierarchies), the Virtual Platform per se is not an answer to all of todays design challenges. But by adding further abstraction to the models, an increasing need for automated mapping, refinement, and model transformations is needed. Formal, static, and dynamic analysis methods are increasingly dependent on platform details, requiring traceability during all design phases. This workshop aims to bring together developers, researchers, and managers from industry and academia to develop a perspective for the future use of Virtual Platforms by exchanging knowledge about current and future requirements and their possible solutions. The workshop will also provide some space for the provision of state of the art and tangible results and session on tool demos.",
	booktitle = "Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow 2012"
}

@inproceedings{Lorenz:2012:NSEHSS,
	author = {Daniel Lorenz and Philipp A. Hartmann and Kim Gr{\"u}ttner and Achim Rettberg},
	title = "Nicht--invasive Simulation des Energieverbrauchs von Hardware--Komponenten auf Systemebene mit SystemC",
	year = 2012,
	month = mar,
	abstract = {Nicht zuletzt durch die zunehmend wachsende algorithmischen Komplexit{\"a}t heutiger einge-- betteter Systeme gewinnt die Betrachtung nicht--funktionaler Eigenschaften dieser Systeme, wie beispielsweise des Energieverbrauchs, immer st{\"a}rker an Bedeutung. Insbesondere in fr{\"u}-- hen Entwurfsphasen, lange vor der Fertigstellung der finalen Hardwareplattform, werden daher Methoden und Werkzeuge zur Analyse und Absch{\"a}tzung der Leistungsaufnahme dringend be-- n{\"o}tigt. In dieser Arbeit wird ein Simulationsframework basierend auf SystemC vorgestellt, welche die Anreicherung von bereits existierenden, funktionalen TLM--2.0--Modellen um solche nicht-- funktionalen Eigenschaften unterst{\"u}tzt. Um auch eine Betrachtung externer IP--Komponenten zu erm{\"o}glichen, kann der hier pr{\"a}sentierte Ansatz ohne Ver{\"a}nderung der einzelnen Bl{\"o}cke verwendet werden. Der (im Detail) unbekannte interne Zustand (und der daraus resultieren-- de Energieverbrauch) der Komponente wird dabei {\"u}ber eine sogenannte Power State--Machine (PSM) angen{\"a}hert. Die Bestimmung des aktuellen Power States erfolgt {\"u}ber eine separat de-- finierte Protocol State--Machine (PrSM), welche durch die nicht--invasive Beobachtung der In-- teraktion des Hardwareblocks mit seiner Umgebung R{\"u}ckschl{\"u}sse auf das aktuelle Verhalten der Komponente erlaubt. Zur Evaluation der Methodik werden unterschiedliche Komponenten beispielhaft modelliert und analysiert.},
	booktitle = "15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
}

@inproceedings{Gruettner:2012:CVPDAPEEESERP,
	author = {Kim Gr{\"u}ttner and Frank Oppenheimer},
	title = "The COMPLEX Virtual Platform Design Approach for Performance and Energy Efficient Embedded Systems: A European Research Perspective",
	year = 2012,
	month = feb,
	organization = "embedded world Conference 2012",
	booktitle = "Embedded SW Development on Virtual Platforms Workshop - Ready for Prime Time?"
}

@inproceedings{Fakih:2012:VLSATAESMP,
	author = {Maher Fakih and Kim Gr{\"u}ttner},
	title = "Virtual--Platform in the Loop Simulation for Accurate Timing Analysis of Embedded Software on Multicore Platforms",
	year = 2012,
	month = feb,
	abstract = "The design of embedded systems with real time requirements is a challenging task. On one side, timing predictability is fundamental for guaranteeing safe system operation. On the other side, complex functional behavior needs to be validated at all refinement levels during the design. For multicore platforms this task becomes even more challenging due to the increased complexity in platform parallelism including access arbitration to shared resources such as memories or peripherals, which impact software execution times. This paper describes a co--simulation based validation method for embedded software implemented on multicore hardware platforms. The co--simulation is realized between Simulink and the SystemC--based SoCLib virtual--platform framework. Simulink is used to implement the system environment and functional model of an embedded control system. SoCLib is used to model a multicore execution platform with shared resources. Our design flow enables code generation and deployment from a Simulink model, and execution of this code on a multicore platform. In addition our virtual--platform model allows the observation of software execution and its timing measurement at a cycle accurate level. We demonstrate the applicability of our method through validation of a real--time critical ignition controller system by running our virtual multicore platform in the loop with the Simulink environmental model.",
	organization = "GI ASIM Fachgruppen {\&}quot;Simulation technischer Systeme{\&}quot; (STS) und {\&}quot;Grundlagen und Methoden in Modellbildung und Simulation{\&}quot; (GMMS)",
	booktitle = "ASIM STS/GMMS Workshop 2012"
}

@inbook{Buecker:2012:MCOMERTN,
	author = {Matthias B{\"u}cker and Kim Gr{\"u}ttner and Philipp A. Hartmann and Ingo Stierand},
	title = "Mapping of Concurrent Object--Oriented Models to Extended Real--Time Task Networks",
	year = 2012,
	pages = "37--54",
	month = jan,
	publisher = "Springer",
	isbn = "978--1--4614--1426--1",
	booktitle = "System Specification and Design Languages -- Selected Contributions from FDL 2010",
	url = "http://www.springer.com/978--1--4614--1426--1",
	doi = "10.1049/ic.2010.0127"
}

@inbook{Gruettner:2012:RPCHSTPAEF,
	title = "Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL Framework",
	booktitle = "System Specification and Design Languages -- Selected Contributions from FDL 2010",
	author = {Kim Gr{\"u}ttner and Kai Hylla and Sven Rosinger and Wolfgang Nebel},
	publisher = "Springer",
	pages = "157--174",
	month = jan,
	year = 2012,
	isbn = "978--1--4614--1426--1",
	doi = "10.1007/978-1-4614-1427-8_10",
	url = "http://www.springer.com/978-1-4614-1426-1"
}

@inbook{Gruettner:2011:AADRRHS,
	title = "ANDRES -- Analysis and Design of Run--Time Reconfigurable, Heterogeneous Systems",
	booktitle = "Reconfigurable Computing -- From FPGAs to Hardware/Software Codesign",
	author = {Kim Gr{\"u}ttner and Philipp A. Hartmann and Andreas Herrholz and Frank Oppenheimer},
	publisher = "Springer",
	pages = 296,
	month = sep,
	year = 2011,
	isbn = "978--1--4614--0060--8",
	abstract = "The main objective of the here presented ANDRES project is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES). Based on a domain--independent formal foundation we combine domain--specific modelling languages and libraries into an integrated framework. This framework allows efficiently using and exploiting adaptivity in embedded systems. The design flow is completed by a methodology for performance analysis and tools for the automatic synthesis of adaptive hardware/software systems",
	doi = "10.1007/978-1-4614-0061-5_8"
}

@inproceedings{Poppen:2011:ISCDPECS,
	author = {Frank Poppen and Roland Koppe and Axel Hahn and Kim Gr{\"u}ttner},
	title = "Impact Simulation of Changes to Development Processes: An ESL Case Study",
	year = 2011,
	month = sep,
	abstract = "Due to the ever increasing need for enhanced productivity in electronic system design new methods and tools in the area of Electronic System Level (ESL) design are becoming more important. Regrettably, the introduction of new methods and tools come at a certain cost, and after its introduction it might be hard to assess the real improvements in the development process. In this paper we present a methodology to model the design process and linked cause--effects based on experience and statistical data. In our case--study we create two models of the same design flow: 1st traditional design flow and 2nd ESL design flow using high--level synthesis. By means of Monte Carlo simulations we automatically process 10.000 probabilistically varied benchmark runs so that the causalities in the modeled development process become clear and the impact of changes to the flow can be predicted prior to their implementation.",
	organization = "ECSI",
	booktitle = "Forum on specification \& Design Languages (FDL) 2011"
}

@inproceedings{Hartmann:2011:NTTOIA,
	title = "Non--intrusive TLM--2.0 Transaction Observation, Interception, and Augmentation",
	author = {Philipp A. Hartmann and Maher A. Fakih and Kim Gr{\"u}ttner},
	organization = "OSCI",
	month = sep,
	year = 2011,
	abstract = "Integrating existing third--party TLM--2.0 components into custom system models frequently require the definition of wrappers to adapt the particular behaviour (or even analysis/tracing capabilities) of such a component to the concrete needs of the overall platform. In this talk, a simple yet powerful framework based on augmentable convenience sockets is presented, greatly reducing the amount of required boiler--plate code in these cases. Transactions are automatically forwarded from/to their wrapped sockets, but can be analysed and even modified easily along the way. The benefits of the approach are demonstrated by externally adding dynamic power-- management capabilities to a pre--existing TLM--2.0 system.",
	booktitle = "24th European SystemC User’s Group Meeting",
	location = "Oldenburg, Germany"
}

@inproceedings{Gruettner:2011:CMMAESD,
	author = {Kim Gr{\"u}ttner and Philipp A. Hartmann and Philipp Reinkemeier and Frank Oppenheimer and Wolfgang Nebel},
	title = "Challenges of Multi-- and Many--Core Architectures for Electronic System--Level Design",
	year = 2011,
	month = jul,
	abstract = "In todays design of embedded systems the software part is increasingly important. Over the last years we have observed a shift from hardware to software added value. With the rise of multi-- and many--core platforms even more complex software systems can be implemented. To efficiently map software applications to such architectures, the impact of platform decisions with respect to the hardware and the software infrastructure (OS, scheduling policies, priorities, mapping) has to be explored in early design phases. In this work, we discuss the challenges of the multi-- and many--core design--space. We give an overview of our existing SystemCTM--based OSSS design flow including software multitasking in system--level models. We propose extensions towards multi-- and many--core platform models and discuss which aspects of the system behaviour can be captured. Since this is work in progress we end up with challenges which have not been solved until now and propose new concepts to overcome the current limitations.",
	doi = "10.1109/SAMOS.2011.6045481",
	booktitle = "SAMOS 2011: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XI)"
}

@inproceedings{Hartmann:2011:FMCOAMP,
	title = "Flexible Mapping of Concurrent Object--Oriented Applications to MPSoC Platforms",
	author = {Philipp A. Hartmann and Kim Gr{\"u}ttner and Frank Oppenheimer and Wolfgang Nebel},
	organization = "ArtistDesign NoE",
	month = jun,
	year = 2011,
	abstract = "The utilisation of processing cores and shared (hardware) resources in today's systems is a key challenge for developing efficient, predictable and correct applications. The cost of explicit and implicit task interaction due to resource sharing can have a tremendous impact on the overall performance of the application. Efficient early exploration and simulation techniques as well as seamless re nement strategies are needed to avoid costly redesigns in late design phases",
	booktitle = "Map2MPSoC 2011 Workshop"
}

@inproceedings{Gruettner:2011:CSSS,
	author = {Kim Gr{\"u}ttner},
	title = "Challenges in SoC System Synthesis",
	year = 2011,
	month = jun,
	abstract = "This panel will start by posing a challenge to the panelists to defend the concept of synthesizing full systems from ESL. The panelists are from industries that use high level synthesis, as well as from industries that develop tools for synthesis. The aim of the panel is to bring out some of the shortcomings, wish lists, and failure and success stories of ESL synthesis.",
	organization = "ECSI",
	booktitle = "ESLsyn 2011"
}

@inproceedings{Hartmann:2011:FGHCRMI,
	title = "A Framework for Generic HW/SW Communication using Remote Method Invocation",
	author = {Philipp A. Hartmann and Kim Gr{\"u}ttner and Philipp Ittershagen and Achim Rettberg},
	organization = "ECSI",
	month = jun,
	year = 2011,
	abstract = "Implementation of communication between different tasks of a concurrent embedded system is a challenging task. The aim of our work is to support the refinement and relocation of tasks onto different execution units, such as processors running different operating system or even dedicated hardware. For this purpose communication should be transparent and as independent as possible from the underlying middleware or embedded operating system. Moreover, communication should also be transparent accros the HW/SW boundary. In this work we present a generic framework for seamless communication of (software) tasks with shared resources, called Shared Objects. Communication is implemented using a method--based interface realizing a Remote Method Invocation (RMI) protocol. Our shared communication resources can either be implemented as dedicated hardware, as shared memory or local tasks. The presented framework is a first step towards the unification of shared resource access based on embedded Linux. The effectiveness of our approach will be evaluated with different task mappings and shared resource access implementation styles.",
	doi = "10.1109/ESLsyn.2011.5952289",
	booktitle = "ESLsyn - The 2011 Electronic System Level Synthesis Conference"
}

@inproceedings{Gruettner:2011:TDDHSPSM,
	author = {Kim Gr{\"u}ttner and Andreas Herrholz and Ulrich K{\"u}hne and Daniel Gro{\ss}e and Achim Rettberg and Wolfgang Nebel and Rolf Drechsler},
	title = "Towards Dependability--aware Design of Hardware Systems using extended Program State Machines",
	year = 2011,
	month = mar,
	abstract = "Due to the continuous shrinking of the transistor sizes which is strongly driven by Moores law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent errors due to manufacturing, process variations, aging as well as soft errors. As a result, the hardware will consist of unreliable components and hence, the development of embedded systems has to change fundamentally. Therefore, we propose a dependability--aware design approach for hardware systems through integrating dependability into a state--of--the--art system--level design language. Our approach is based on SystemC and extends the Program State Machine model to explicitly observe, diagnose, and compensate faulty behavior. Different compensation mechanisms like run--time reconfiguration or mechanisms for error propagation can be used by the designer during refinement. They are controlled by a new exception--like mechanism. Furthermore, our approach aims to integrate functional verification as well as dependability verification with respect to given fault models.",
	organization = "In conjunction with 14th IEEE International Symposium on Object/Component/Service--oriented Real--time Distributed Computing",
	isbn = "978-0-7695-4377-2",
	doi = "10.1109/ISORCW.2011.27",
	booktitle = "SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems"
}

@inproceedings{Hartmann:2011:FGHCRMI1,
	author = {Philipp A. Hartmann and Philipp Ittershagen and Kim Gr{\"u}ttner and Frank Oppenheimer and Achim Rettberg},
	title = "A Framework for Generic HW/SW Communication using Remote Method Invocation",
	year = 2011,
	month = mar,
	booktitle = "Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2011)"
}

@inproceedings{Gruettner:2011:ETPAVPHS,
	author = {Kim Gr{\"u}ttner and Kai Hylla and Sven Rosinger and Philipp A. Hartmann and Wolfgang Nebel},
	title = "Enabling Timing and Power Aware Virtual Prototyping of HW/SW Systems",
	year = 2011,
	month = mar,
	abstract = "We propose the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SW systems. Our proposed flow combines system--level timing and power estimation techniques available in commercial tools with platform--based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C++ specification. These prototypes are enriched by static and dynamic power values as well as execution times. They allow a trade--off between different platforms, mapping alternatives, and optimization techniques, based on domainspecific workload scenarios.",
	organization = "In conjunction with Design, Automation, and Test in Europe Conference (DATE) 2011",
	booktitle = "Workshop on Micro Power Management for Macro Systems on Chip (uPM2SoC)"
}

@inproceedings{Ferrero:2011:UCDFSDA,
	author = {Francisco Ferrero and Kim Gr{\"u}ttner and Fernando Herrera and Gianluca Palermo and Bart Vanthournout and Emmanuel Vaumorin},
	title = "Using the COMPLEX Design Flow for Space Domain Applications",
	year = 2011,
	month = mar,
	organization = "In conjunction with Design, Automation, and Test in Europe Conference (DATE) 2011",
	booktitle = "Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2011)"
}

@inproceedings{Gruettner:2011:CEFTPARPHS,
	author = {Kim Gr{\"u}ttner},
	title = "The COMPLEX ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems",
	year = 2011,
	month = mar,
	abstract = "Consideration of an embedded systems timing behavior and power consumption at system--level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard and software as well as IP components. But prediction of the composed system behavior can hardly be made. In this session we present the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SW systems. Our proposed flow combines system--level timing and power estimation techniques available in commercial tools with platform--based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C++ specification. These prototypes are enriched by static and dynamic power values as well as execution times. They allow a trade--off between different platforms, mapping alternatives, and optimization techniques, based on domain--specific workload scenarios. The proposed flow will be implemented in the COMPLEX FP7 European integrated project (http://complex.offis.de).",
	booktitle = "Design, Automation \& Test in Europe (DATE) 2011"
}

@inproceedings{Ittershagen:2011:EgTHO,
	author = {Philipp Ittershagen and Philipp A. Hartmann and Kim Gr{\"u}ttner and Achim Rettberg},
	title = "Ein generisches Treiber--Framework zur HW/SW--Kommunikation mittels OSSS--RMI",
	year = 2011,
	month = feb,
	abstract = {Die Realisierung der Kommunikation zwischen verschiedenen Tasks ist eine entscheidende Aufgabe bei der Entwicklung paralleler, eingebetteter Systeme. Wird im Laufe der Verfeinerung eines Systems die Zuordnung einzelner Komponenten auf unterschiedliche Berechnungseinheiten (Hardware, Software) ver{\"a}ndert, werden oftmals aufw{\"a}ndige Design{\"a}nderungen n{\"o}tig. In dieser Arbeit wird ein generisches Framework vorgestellt, um die Kommunikation von (Software--) Tasks mit sogenannten Shared Objects durchg{\"a}ngig zu erm{\"o}glichen. Die Kommunikation wird dabei {\"u}ber eine methodenbasierte Schnittstelle mit Hilfe des Remote Method Invocation (RMI) Protokolls realisiert. Die Objekte k{\"o}nnen dabei als dedizierte Hardware, in gemeinsam genutztem Speicher oder lokal zugreifbar vorliegen -- durch das hier vorgestellte Framework wird der Zugriff vereinheitlicht. Die Effektivit{\"a}t des Ansatzes wird anhand eines Beispiels evaluiert.},
	booktitle = "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2011)"
}

@inproceedings{Gruettner:2010:TSSSC,
	author = {Kim Gr{\"u}ttner and Henning Kleen and Frank Oppenheimer and Achim Rettberg and Wolfgang Nebel},
	title = "Towards a Synthesis Semantics for SystemC Channels",
	year = 2010,
	month = oct,
	booktitle = "International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS)"
}

@inproceedings{Hartmann:2010:DRSMAS,
	author = {Philipp A. Hartmann and Kim Gr{\"u}ttner and Achim Rettberg and Ina Podolski},
	title = "Distributed Resource--Aware Scheduling for Multi--Core Architectures with SystemC",
	year = 2010,
	month = sep,
	doi = "10.1007/978-3-642-15234-4_18",
	booktitle = "7th IFIP Conference on Distributed and Parallel Embedded Systems (DIPES)"
}

@inproceedings{Gruettner:2010:TEFTPARPHS,
	author = {Kim Gr{\"u}ttner and Kai Hylla and Sven Rosinger and Wolfgang Nebel},
	title = "Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems",
	year = 2010,
	month = sep,
	doi = "10.1049/ic.2010.0129",
	booktitle = "Forum on Specification \& Design Languages (FDL)"
}

@inproceedings{Bueker:2010:MCOMERTN,
	author = {Matthias B{\"u}ker and Kim Gr{\"u}ttner and Philipp A. Hartmann and Ingo Stierand},
	title = "Mapping of Concurrent Object--Oriented Models to Extended Real--Time Task Networks",
	year = 2010,
	month = sep,
	abstract = "For checking the temporal behaviour of embedded systems, real--time scheduling analysis based on abstract, formal models is a well--established method. A major difficulty for such analytical models in practical use--cases is the non--trivial representation of a real implementation model. To overcome this limitation we propose a formal mapping of a concurrent, object--oriented, executable implementation model with explicit shared resources to a real--time task network with functional extensions. The mapping starts from a C++ subset and maps the functional behaviour based on externally observable synchronisation events. The proposed mapping allows to check the implementation model against functional and temporal requirements, like local and end--to--end deadlines.",
	doi = "10.1049/ic.2010.0127",
	booktitle = "Forum on Specification \& Design Languages (FDL)"
}

@inproceedings{Montenegro:2010:SANPPD,
	author = {Sergio Montenegro and Benjamin Vogel and Vladimir Petrovic and Gunter Schoof and Andreas Herrholz and Kim Gr{\"u}ttner},
	title = "Spacecraft Area Network (SCAN) for Plug and Play of Devices",
	year = 2010,
	month = may,
	organization = "ESA",
	booktitle = "Small Satellite Systems and Services - The 4S Symposium 2010"
}

@inproceedings{Hartmann:2010:EPCPO,
	title = "Exploiting Parallel Computing Platforms with OSSS",
	author = {Philipp A. Hartmann and Kim Gr{\"u}ttner and Frank Oppenheimer},
	organization = "edaCentrum",
	month = may,
	year = 2010,
	booktitle = "edaWorkshop 2010"
}

@inproceedings{Popp:2010:SSMSEHA,
	title = "SystemC--AMS SDF Model Synthesis for Exploration of Heterogeneous Architectures",
	author = {Andreas Popp and Andreas Herrholz and Kim Gr{\"u}ttner and Yannick {Le Moullec} and Peter Koch and Wolfgang Nebel},
	organization = "IEEE",
	month = apr,
	year = 2010,
	doi = "10.1109/DDECS.2010.5491801",
	booktitle = "IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)"
}

@inproceedings{Oppenheimer:2010:AADRS,
	title = "ANDRES -- Analysis and Design of run--time Reconfigurable, heterogeneous Systems",
	author = {Kim Gr{\"u}ttner; Frank Oppenheimer},
	month = mar,
	year = 2010,
	booktitle = "W1: The European landscape of reconfigurable computing: Lessons learned, new perspectives and innovations, DATE 2010"
}

@inproceedings{Hartmann:2010:EPCPO1,
	author = {Philipp A. Hartmann and Kim Gr{\"u}ttner and Frank Oppenheimer and Achim Rettberg},
	title = "Exploiting Parallel Computing Platforms with OSSS",
	year = 2010,
	month = mar,
	booktitle = "W3: Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, DATE 2010"
}

@inbook{Schallenberg:2009:POF,
	author = {Andreas Schallenberg and Wolfgang Nebel and Andreas Herrholz and Philipp A. Hartmann and Kim Gr{\"u}ttner and Frank Oppenheimer},
	title = "POLYDYN Object--oriented modelling and synthesis targeting dynamically reconfigurable FPGAs",
	year = 2009,
	month = dec,
	publisher = "Springer",
	isbn = "978--90--481--3484--7",
	booktitle = "Dynamically Reconfigurable Systems Architectures, Design Methods and Applications",
	doi = "10.1007/978-90-481-3485-4_7"
}

@techreport{Wenninger:2009:OMFAHES,
	author = {J. Wenninger and M. Damm and J. Haase and J. Ou and Kim Gr{\"u}ttner and Philipp A. Hartmann and Andreas Herrholz and F. Herrera and I. Sander and J. Zhu},
	title = "Overall Modelling Framework for AHES (Adaptive Heterogeneous Embedded Systems)",
	year = 2009,
	month = aug
}

@manual{Gruettner:2008:OLSSLMSOM,
	author = {Kim Gr{\"u}ttner and Andreas Herrholz and Philipp A. Hartmann and Andreas Schallenberg and Claus Brunzema},
	title = "OSSS -- A Library for Synthesisable System Level Models in SystemC(TM) -- The OSSS 2.2.0 Manual",
	year = 2008,
	month = sep
}

@techreport{Gruettner:2008:M,
	author = {Kim Gr{\"u}ttner and Andreas Herrholz and Philipp A. Hartmann},
	title = "Modelling of run--time reconfigurable hardware -- final library elements",
	year = 2008,
	month = jan
}

@inproceedings{Oppenheimer:2007:OAMRSHS,
	author = {Frank Oppenheimer and Kim Gr{\"u}ttner},
	title = "OSSS: An Approach for Modelling, seamless Refinement, and Synthesis of HW/SW SoC",
	year = 2007,
	month = sep,
	organization = "European SystemC User Group",
	booktitle = "16. European User Group Meeting"
}

@manual{Brunzema:2007:OLSSLMSO,
	author = {Claus Brunzema and Cornelia Grabbe and Kim Gr{\"u}ttner and Philipp A. Hartmann and Andreas Herrholz and Henning Kleen and Frank Oppenheimer and Andreas Schallenberg and Christian Stehno and Thorsten Schubert},
	title = "OSSS -- A Library for Synthesisable System Level Models in SystemC(TM) -- A tutorial for OSSS 2.0",
	year = 2007,
	month = jan,
	abstract = "This tutorial is for people who want to learn about OSSS and the OSSS synthesis flow."
}

@inproceedings{Grüttner_2006,
	abstract = "In this paper we present OSSS-Channels, a concept for modelling and synthesis of communication in SystemC. The OSSS-Channel provides mechanisms for the connection of multiple master and slave modules assisted by an automatic generation of the interconnect network. Supported interconnection architectures are point to point, shared bus or crossbar switch. Besides the architecture the OSSS-Channel provides mechanisms for specifying communication protocols and user defined arbitration mechanisms. By the provision of an abstract high level method interface, channel implementations describing different communication architectures with different communication protocols can be stored in a library for easy reuse. Due to the usage of an object oriented extension of the SystemC synthesis subset called OSSS our channel enables the transfer of abstract data types. The modelling concept and synthesis semantics will be illustrated by simple examples. The applicability of our approach will be shown in the context of SystemC TLM and IP integration. Finally we will briefly outline our aspired synthesis design flow.",
	author = {Kim Gr{\"u}ttner and Cornelia Grabbe and Frank Oppenheimer and Wolfgang Nebel},
	booktitle = "Tagungsband: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen",
	editor = "Bernd Straube and Martin Freibothe",
	isbn = "3-9810287-1-6",
	language = "englisch",
	month = feb,
	organization = {Fachgruppe 3 und 4 der RSS Kooperationsgemeinschaft Rechnergest{\"u}tzter Schaltungs- und Systementwurf der GI, ITG und GMM},
	pages = "38--47",
	series = "9. ITG/GI/GMM Workshop",
	title = "Modelling and Synthesis of Communication Using OSSS-Channels",
	year = 2006
}