Synchronous Parallel Register

This design shows a very simple register collection in SystemC. It's a fully parallel register of a parametrised size (and datatype), with one-hot encoded write-enable signals and a synchronous reset.

It is implemented with an SC_METHOD() process for best simulation performance. This is the simplest implementation, since no internal FSM is required.

#include <systemc.h>
 
template< typename DataType, unsigned Size = 8 >
SC_MODULE( sync_register )
{
  typedef DataType  value_type;
 
  sc_in<bool> clock;
  sc_in<bool> reset;
  /* ----- input ports ----- */
  sc_in< sc_uint<Size> >     in_wen;
  sc_in< value_type >        in_data;
 
  /* ----- output ports ----- */
  sc_out< value_type >       data[Size];
 
  /* ----- constructor ----- */
  SC_CTOR( sync_register )
  {
     /* ----- process definitions ----- */
     SC_METHOD( processing );
     sensitive << clock.pos();
  }
 
private:
  /* ----- process(es) ----- */
  void processing();
 
}; // sync_register
 
/* ----- process body ----- */
template< typename DataType, unsigned Size >
void
sync_register<DataType,Size>::processing()
{
  sc_uint<10> wen  = in_wen.read();
 
  for(unsigned i=0; i<Size; ++i)
  {
    if( reset.read() ) {
      data[i].write( 0 );
    } else if( wen[i].to_bool() ) {
      data[i].write( in_data );
    }
  }
} // sync_register::processing()
 
/* ----- sc_main() -----
 *
 * We need an explicit main, since we have to
 * instantiate our templated module here.
 */
int sc_main( int, char*[] )
{
  sync_register< sc_uint<32>, 4 > top( "top" );
  return 0;
}