User Tools

Site Tools


bib:2015

@inproceedings{rgoergen_dvcon_europe_2015,

Author = {Ralph G{\"o}rgen and Philipp A. Hartmann and Wolfgang Nebel},
Title = {Automated SystemC Model Instantiation with modern C++ Features and sc{\_}vector},
Year = {2015},
Month = {11},
Booktitle = {Proceedings of DVCon Europe 2015},
Organization = {Accellera Systems Initiative},
File = {rgoergen_dvcone_2015_sc_vector.pdf}

}

@inproceedings{ittershagen_mc_modelling_2015,

  author = {Philipp Ittershagen and and Kim Gr{\"u}ttner and Wolfgang Nebel},
  title = {Mixed-Criticality System Modelling with Dynamic Execution Mode Switching},
  year = {2015},
  month = {9},
  booktitle = {Proceedings of the Forum on Specification and Design Languages (FDL'2015)},
  url = {http://ecsi.org/fdl},
  abstract = {In this paper, an executable system model for performing a functional simulation while observing the dynamic effects of mixed-criticality requirements regarding applications with different levels of assurance is proposed. The model provides the expression of dynamic execution modes and execution time estimates on each criticality level of the system. In a refinement step, it is possible to observe the effects of scheduling policies, dynamic criticality-, and execution mode switches on the functional behaviour of the system in a trace-based, simulative manner. An early evaluation of a quadrocopter platform consisting of a safety critical flight control application and a video-based, performance critical object detection is used to demonstrate the applicability of the design flow. Simulation results indicate that by defining multiple execution modes of the object detection algorithm, the run-time utilisation feedback allows the algorithm to run in a high-quality mode for more than 50% of the time, thereby increasing the overall system utilisation by two thirds compared to a static resource utilisation analysis.},
  file = {2015_ittershagen_mc_modelling.pdf}

}

@inproceedings{ittershagen_sw_performance_2015,

  author = {Philipp Ittershagen and Philipp A. Hartmann and Kim Gr{\"u}ttner and Wolfgang Nebel},
  title = {A Workload Extraction Framework for Software Performance Model Generation},
  year = {2015},
  month = {1},
  abstract = {The early performance evaluation of complex platforms and software stacks requires fast and sufficiently accurate workload representations.  In the literature, two different approaches have been proposed: Host--based
    simulation with abstract performance annotations, enabling fast and functional simulations with limited architectural accuracy, and abstract workload models (or traffic generators) with more detailed platform resource usage patterns.
      In this work, we present an approach for automatic workload extraction from functional application code, combining the benefits of both approaches.  First, the algorithmic behaviour of the embedded software
      is characterised statically both in terms of target processor usage and target memory access patterns, resulting in an abstracted, control flow--aware workload model.  Secondly, this model can be used on the target architecture itself as well as within a host--based simulation environment. We demonstrate the effectiveness of our approach by running our performance model on a virtual platform with and without a target Instruction Set Simulator (ISS) and comparing the simulation traces with the unaltered target processor binary execution.},
  booktitle = {7th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO'15)},
  url = {http://www.rapido.deib.polimi.it/},
  file = {2015_ittershagen_workload_extraction.pdf}

}

@INPROCEEDINGS{sschreiner:2015:mbmvm,

Author = {Schreiner, S{\"o}ren and Gr{\"u}ttner, Kim and Rosinger, Sven and Nebel, Wolfgang},
Title = {Ein Verfahren zur Bestimmung eines Powermodells von Xilinx MicroBlaze MPSoCs zur Verwendung in Virtuellen Plattformen},
Year = {2015},
Month = {03},
Abstract = {Durch die Einführung von Multi-Processor-System-on-Chips werden die steigenden Anforderungen an die Performanz für moderne Eingebettete Systeme erfüllt. Oft sind diese aber im mobilen Einsatz und müssen insbesondere Anforderungen an ihre Leistungsaufnahme erfüllen. Die vorliegende Arbeit stellt einen Ansatz vor, wie durch Charakterisierung einer realen Hardware eine Virtuelle Plattform des gleichen Systems mit gemessenen Verlustleistungsdaten annotiert werden kann. So können echte Anwendungen auf der Virtuellen Plattform ausgeführt und Vorhersagen über die Leistungsaufnahme des realen Systems getätigt werden. Zur ersten Evaluation des beschriebenen Ansatzes wurde ein Xilinx MicroBlaze MPSoC Designs auf einem FPGA implementiert, mit Hilfe von Micro-Benchmarks dessen Verlustleistung charakterisiert und daraus ein Power State Machine Modell erstellt. Dieses wurde in einer OVP-basierten Virtuellen Plattform des gleichen Designs integriert und dessen Verlustleistungsvorhersage in einer Co-Simulation mit der Messung der Verlustleistung am FPGA-Design verglichen. Für die durchgeführten Experimente hat sich ein akkumulierter Fehler kleiner als 1% ergeben.},
Booktitle = {18. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015)}

}

@INPROCEEDINGS{jwalter_large_scale_mapping_2015, Author = {Walter, J{\“o}rg and Nebel, Wolfgang}, Title = {Energy–Aware Mapping and Scheduling of Large–Scale Macro Data–Flow Applications}, Year = {2015}, Month = {01}, Abstract = {Predicting the performance of parallel programs for large–scale parallel platforms is difficult due to the disparity between development system and target platform. Additionally, energy efficiency is becoming a universal concern, and platforms move towards highly heterogeneous systems containing GPUs, FPGAs, and other unconventional processing elements.In this paper we propose a static macro data–flow mapping and scheduling tool that is able to handle large parallel applications targeting heterogeneous platforms. It optimizes overall run time and energy consumption at the same time with a user–configurable cost function, allowing a selectable trade–off between both properties.}, Booktitle = {1st International Workshop on Investigating Dataflow in Embedded Computing Architecture (IDEA 2015)}, file = {2015_walter_large_scale_mapping.pdf} }

@COMMENT{Bibtex file generated on 2014–12–11 }

bib/2015.txt · Last modified: 2015-11-27 18:15 by Ralph Görgen