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@InProceedings{ Sauppe:2013:DIPDSL,

author = "Matthias Sauppe and Thomas Horn and Erik Markert and Ulrich Heinkel and Daniel Lorenz and Kim Gr{\"u}ttner and Hans-Werner Sahm and Klaus-Holger Otto",
Title = "A Database for the Integration of Power Data on System Level",
Year = "2013",
Month = "07",
abstract = "Using state of the art design methods, advanced calculation of system power budgets is a major challenge. Currently, system design methods do not offer sufficient means for supporting energy awareness and efficiency throughout the complete system design process. In this paper, we present a power database for storing and predicting power data of integrated systems across abstraction levels, starting at system level and going all the way down to gate level. Our approach bases on the definition of multiple use cases per component, which allows for accurate power prediction of hierarchically defined systems al-ready during the system-level design stage. This leads to reduced design costs as early power-affecting design decisions can be made on a sound basis. For evaluation, use cases for a commercially used network router component and its subcomponents were generated and power-simulated. After applying the results to the power database, we show that use case based power prediction on system level can be highly accurate, as our example calculation results in an error of less than five percent.",
Organization = "IEEE"
project = "enersave"


@InProceedings{ Ittershagen:2013:HRTSMCEO,

author = "Philipp Ittershagen and Philipp A. Hartmann and Kim Gr{\"u}ttner and Achim Rettberg",
Title = "Hierarchical Real-Time Scheduling in the Multi-Core Era - An Overview",

booktitle = {IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)}, year = {2013}, month = {June}, pages = {1-10}, doi = {10.1109/ISORC.2013.6913241},

abstract = "With the accelerating pervasiveness of multi-core platforms in the embedded domains and the on-going need for more computational power and increased integration, multi-core scheduling for real-time and mixed-critical applications is an active research topic. In this paper, we give an overview on the history and the current state-of-the-art on multi-core real-time scheduling. A special focus is put on shared resource access protocols and hierarchical scheduling approaches, both of which are increasingly important due to the higher spatial integration and stronger coupling between the different subsystems, both on the application and on the multi-core architectural level. Moreover, hierarchical scheduling is a promising approach in the area of mixed-criticality systems to enable composability and segregation, which is needed to cope with the complexity of such systems. This survey will be of interest to researchers and practitioners in the field of real-time scheduling for multi-core systems."
project = "aramis",
      file = "ittershagen-sort-mc-scheduling.pdf"


@InProceedings{ Fakih:2013:TPASMSBAUMC,

author = "Fakih Maher and Kim Gr{\"u}ttner and Martin Fr{\"a}nzle and Achim Rettberg",
Title = "Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking",
Year = "2013",
Month = "03",
abstract = "The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model- checking based approach will be described which allows us to guarantee timing bounds of multiple Synchronous Data Flow Graphs (SDFG) running on shared-bus multicore architectures. Our approach utilizes Timed Automata (TA) as a common semantic model to represent software components (SDF actors) and hardware components of the multicore platform. These TA are explored using the UPPAAL model-checker for providing the timing guarantees. Our approach shows a significant precision improvement compared with the worst-case bounds estimated based on maximal delay for every bus access. Furthermore, scalability is examined to demonstrate analysis feasibility for small parallel systems. ",
Publisher = "European Design and Automation Association",
Series = "DATE '13",
Address = "3001 Leuven, Belgium, Belgium",
Booktitle = "Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2013"
project = "motorbrain"


@InProceedings{ Ittershagen:2013:ABKMPS,

author = "Philipp Ittershagen and Philipp A. Hartmann and Kim Gr{\"u}ttner and Wolfgang Nebel",
Title = "Ansatz zur Bewertung der HW/SW-Kommunikation in asymmetrischen Multi-Prozessor-Systemen",
Year = {2013},
Pages = {197--208},
Month = {3},
abstract = "Heutige Multi-Prozessor-Systeme verf{\"u}gen {\"u}ber
komplexe Kommunikations- und Speicherhierarchien zur Synchronisation
und zum Nachrichtenaustausch. Hinzu kommt eine Vielzahl von
anwendungsspezifischen Hardwarekomponenten, die von unterschiedlichen
Prozessoren gemeinsam genutzt werden k{\"o}nnen. Um die
Hardwarekomplexit{\"a}t vor dem Anwender mit Hilfe eines geeigneten
Programmiermodells zu verbergen, wird auch die Software-Architektur
zunehmend m{\"a}chtiger. Zur Analyse der funktionalen und
extra-funktionalen Einfl{\"u}sse der Software-Architektur und
Konfiguration im Zusammenspiel mit der Hardwareplattform werden
fortgeschrittene Analysemethoden und werkzeuge ben{\"o}tigt. Zu diesem
Zweck wird im Rahmen dieser Arbeit ein flexibles Analysemodell,
basierend auf einem parallelen Programmiermodell, vorgestellt. Das
vorgeschlagene Modell, in Kombination mit einer virtuellen
Hardwareplattform des Zielsystems, ist in der Lage das Zeitverhalten
unterschiedlicher Workloadmodelle unter Ber{\"u}cksichtigung von
RTOS-, Treiber- und Kommunikationsartefakten zu charakterisieren. Zur
Evaluation wird ein Linux-basiertes Betriebssystem auf einer ARM
Dual-Core Plattform mit einer von beiden Prozessoren genutzten
Hardware-Ressource bzgl. des Antwortzeitverhaltens unter verschiedenen
Workload-, Betriebssystem- und Plattformparametern untersucht.",

Booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2013)}, Organization = {Universit{\“a}t Rostock},

project = "aramis",
      file = "ittershagen-mbmv2013-perf-eval.pdf"


@InProceedings{ Hylla:2013:EPTECHBAGCM,

author = "Kai Hylla and Philipp A. Hartmann and Domenik Helms and Wolfgang Nebel",
Title = "Early Power \& Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros",
Year = "2013",
Month = "03",
abstract = "In this paper we present a technique for automatically estimating power and timing of full-custom hardware blocks, such as co-processors or hardware accelerators from algorithmic descriptions. The required characterisation is performed on a cycle-accurate functional description at register transfer level, which is obtained from a high-level synthesis. Characterisation results are used for generating a power and timing aware high-level simulation model. As an abstraction step, combinatorial macros are identified and characterised automatically. Characterisation takes place using RT-level power models, providing accurate estimates. Using the characterised macros, a power and timing annotated high-level simulation model is generated. This C++-based virtual prototype allows a fast, yet accurate estimation of the given design. Having a total error of about 3.6 {\%} we achieve a speed-up of approximately 516x compared to an RT-level estimation, while giving cycle-accurate timing and power estimates."
project = "complex"


@Misc{ Gruettner:2013:PEMACVP,

author = "Kim Gr{\"u}ttner and Philipp A. Hartmann and Frank Oppenheimer",
Title = "Performance and Energy Modeling and Analysis in COMPLEX Virtual Platform",
Year = "2013",
Month = "02"
project = "complex"


@INPROCEEDINGS{jwalter_archc_tlm2_2013, Author = {Walter, J{\”o}rg and Lenhardt, J{\“o}rg and Schiffmann, Wolfram}, Title = {SoC Performance Evaluation with ArchC and TLM–2.0}, Year = {2013}, Month = {07}, Url = {}, abstract = {ArchC is an architecture description language that provides instruction set level simulation and binary tool chain generation. It is based on SystemC and can communicate with other SystemC components using transaction level modeling (TLM). In this article we present an upgrade of ArchC that allows TLM-2.0 usage and makes it available in timed simulations. These extensions enable performance evaluation of complete System-on- Chip designs built around an ArchC processor model. As a proof-of-concept, we examine various TLM-connected memory hierarchies. We outline how model designers can use a combination of fast functional simulation and slow timed simulation to determine an optimal system architecture for a given workload. }, booktitle = {8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC 2013)}, file = {2013_walter_archc_tlm2.pdf} }


author = {Reinkemeier, Philipp and Ittershagen, Philipp and Stierand,
Ingo and Hartmann, Philipp A. and Henkler, Stefan and Gr{\"u}ttner, Kim},
title = {{Seamless} {Segregation} for {Multi-Core} {Systems}},
year = 2013,
month = sep,
file = {},
Institution = {OFFIS}


bib/2013.txt · Last modified: 2015-01-30 11:07 by Philipp Ittershagen