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bib:2011

@InBook{ Gruettner:2011:AADRRHS,

title = "ANDRES -- Analysis and Design of Run--Time Reconfigurable, Heterogeneous Systems",
booktitle = "Reconfigurable Computing -- From FPGAs to Hardware/Software Codesign",
author = {Kim Gr{\"u}ttner and Philipp A. Hartmann and Andreas Herrholz and Frank Oppenheimer},
publisher = "Springer",
pages = "296",
month = "09",
year = "2011",
isbn = "978--1--4614--0060--8",
abstract = "The main objective of the here presented ANDRES project is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES). Based on a domain--independent formal foundation we combine domain--specific modelling languages and libraries into an integrated framework. This framework allows efficiently using and exploiting adaptivity in embedded systems. The design flow is completed by a methodology for performance analysis and tools for the automatic synthesis of adaptive hardware/software systems",
doi = "10.1007/978-1-4614-0061-5_8",
Project = "ANDRES"

}

@InProceedings{ Poppen:2011:ISCDPECS,

Author = {Frank Poppen and Roland Koppe and Axel Hahn and Kim Gr{\"u}ttner},
Title = "Impact Simulation of Changes to Development Processes: An ESL Case Study",
Year = "2011",
Month = "09",
abstract = "Due to the ever increasing need for enhanced productivity in electronic system design new methods and tools in the area of Electronic System Level (ESL) design are becoming more important. Regrettably, the introduction of new methods and tools come at a certain cost, and after its introduction it might be hard to assess the real improvements in the development process. In this paper we present a methodology to model the design process and linked cause--effects based on experience and statistical data. In our case--study we create two models of the same design flow: 1st traditional design flow and 2nd ESL design flow using high--level synthesis. By means of Monte Carlo simulations we automatically process 10.000 probabilistically varied benchmark runs so that the causalities in the modeled development process become clear and the impact of changes to the flow can be predicted prior to their implementation.",
Organization = "ECSI",
booktitle = "Forum on specification \& Design Languages (FDL) 2011",
Project = "COMPLEX IMPACT"

}

@InProceedings{ Hartmann:2011:NTTOIA,

title = "Non--intrusive TLM--2.0 Transaction Observation, Interception, and Augmentation",
author = {Philipp A. Hartmann and Maher A. Fakih and Kim Gr{\"u}ttner},
organization = "OSCI",
month = "09",
year = "2011",
abstract = "Integrating existing third--party TLM--2.0 components into custom system models frequently require the definition of wrappers to adapt the particular behaviour (or even analysis/tracing capabilities) of such a component to the concrete needs of the overall platform. In this talk, a simple yet powerful framework based on augmentable convenience sockets is presented, greatly reducing the amount of required boiler--plate code in these cases. Transactions are automatically forwarded from/to their wrapped sockets, but can be analysed and even modified easily along the way. The benefits of the approach are demonstrated by externally adding dynamic power-- management capabilities to a pre--existing TLM--2.0 system.",
booktitle = "24th European SystemC User’s Group Meeting",
location = "Oldenburg, Germany",
Project = "COMPLEX"

}

@InProceedings{ Gruettner:2011:CMMAESD,

Author = {Kim Gr{\"u}ttner and Philipp A. Hartmann and Philipp Reinkemeier and Frank Oppenheimer and Wolfgang Nebel},
Title = "Challenges of Multi-- and Many--Core Architectures for Electronic System--Level Design",
Year = "2011",
Month = "07",
abstract = "In todays design of embedded systems the software part is increasingly important. Over the last years we have observed a shift from hardware to software added value. With the rise of multi-- and many--core platforms even more complex software systems can be implemented. To efficiently map software applications to such architectures, the impact of platform decisions with respect to the hardware and the software infrastructure (OS, scheduling policies, priorities, mapping) has to be explored in early design phases. In this work, we discuss the challenges of the multi-- and many--core design--space. We give an overview of our existing SystemCTM--based OSSS design flow including software multitasking in system--level models. We propose extensions towards multi-- and many--core platform models and discuss which aspects of the system behaviour can be captured. Since this is work in progress we end up with challenges which have not been solved until now and propose new concepts to overcome the current limitations.",
doi = "10.1109/SAMOS.2011.6045481",
booktitle = "SAMOS 2011: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XI)",
Project = "Complex"

}

@InProceedings{ Nebel:2011:TTRA,

Author = "Wolfgang Nebel",
Title = "Technology Transfer from Research to Application and vice versa",
Year = "2011",
Month = "07",
booktitle = "NGI-Kongress",
Project = "none"

}

@InProceedings{ Hartmann:2011:FMCOAMP,

title = "Flexible Mapping of Concurrent Object--Oriented Applications to MPSoC Platforms",
author = {Philipp A. Hartmann and Kim Gr{\"u}ttner and Frank Oppenheimer and Wolfgang Nebel},
organization = "ArtistDesign NoE",
month = "06",
year = "2011",
abstract = "The utilisation of processing cores and shared (hardware) resources in today's systems is a key challenge for developing efficient, predictable and correct applications. The cost of explicit and implicit task interaction due to resource sharing can have a tremendous impact on the overall performance of the application. Efficient early exploration and simulation techniques as well as seamless re nement strategies are needed to avoid costly redesigns in late design phases",
booktitle = "Map2MPSoC 2011 Workshop",
Project = "ArtistDesign COMPLEX"

}

@InProceedings{ Gruettner:2011:CSSS,

Author = {Kim Gr{\"u}ttner},
Title = "Challenges in SoC System Synthesis",
Year = "2011",
Month = "06",
abstract = "This panel will start by posing a challenge to the panelists to defend the concept of synthesizing full systems from ESL. The panelists are from industries that use high level synthesis, as well as from industries that develop tools for synthesis. The aim of the panel is to bring out some of the shortcomings, wish lists, and failure and success stories of ESL synthesis.",
Organization = "ECSI",
booktitle = "ESLsyn 2011",
Project = "COMPLEX"

}

@InProceedings{ Hartmann:2011:FGHCRMI,

title = "A Framework for Generic HW/SW Communication using Remote Method Invocation",
author = {Philipp A. Hartmann and Kim Gr{\"u}ttner and Philipp Ittershagen and Achim Rettberg},
organization = "ECSI",
month = "06",
year = "2011",
abstract = "Implementation of communication between different tasks of a concurrent embedded system is a challenging task. The aim of our work is to support the refinement and relocation of tasks onto different execution units, such as processors running different operating system or even dedicated hardware. For this purpose communication should be transparent and as independent as possible from the underlying middleware or embedded operating system. Moreover, communication should also be transparent accros the HW/SW boundary. In this work we present a generic framework for seamless communication of (software) tasks with shared resources, called Shared Objects. Communication is implemented using a method--based interface realizing a Remote Method Invocation (RMI) protocol. Our shared communication resources can either be implemented as dedicated hardware, as shared memory or local tasks. The presented framework is a first step towards the unification of shared resource access based on embedded Linux. The effectiveness of our approach will be evaluated with different task mappings and shared resource access implementation styles.",
doi = "10.1109/ESLsyn.2011.5952289",
booktitle = "ESLsyn - The 2011 Electronic System Level Synthesis Conference",
Project = "COMPLEX"

}

@InProceedings{ Bannow:2011:ATMMSA,

Author = {Nico Bannow and Ralph G{\"o}rgen and Wolfgang Nebel},
Title = "Automatic Transformation of MATLAB/Simulink Models to SystemC AMS",
Year = "2011",
Month = "05",
abstract = "To satisfy the reliability requirements of today's embedded systems, such as automotive electronics, design validation at system level is essential. A common way to do this is simulation. One of the major challenges in this context arises from the fact that different parts of a system are modeled in different modeling environments, e.{{\$}\backslash{\$}},g. digital hardware components are implemented in hardware description languages like VHDL or SystemC, whereas an overall system model is done in multi--domain environments like Simulink. Hence, to enable system level verification, techniques for an efficient co--simulation of those modeling environments are necessary. In this paper, we present an automated flow for integrating hardware descriptions into Simulink simulations. The model transformation strategy will be described and evaluated with two industrial automotive electronics hardware designs.",
Organization = "OSCI",
booktitle = "SystemC AMS Day",
Project = "RapidMPSoC"

}

@InProceedings{ Gruettner:2011:TDDHSPSM,

Author = {Kim Gr{\"u}ttner and Andreas Herrholz and Ulrich K{\"u}hne and Daniel Gro{\ss}e and Achim Rettberg and Wolfgang Nebel and Rolf Drechsler},
Title = "Towards Dependability--aware Design of Hardware Systems using extended Program State Machines",
Year = "2011",
Month = "03",
abstract = "Due to the continuous shrinking of the transistor sizes which is strongly driven by Moores law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent errors due to manufacturing, process variations, aging as well as soft errors. As a result, the hardware will consist of unreliable components and hence, the development of embedded systems has to change fundamentally. Therefore, we propose a dependability--aware design approach for hardware systems through integrating dependability into a state--of--the--art system--level design language. Our approach is based on SystemC and extends the Program State Machine model to explicitly observe, diagnose, and compensate faulty behavior. Different compensation mechanisms like run--time reconfiguration or mechanisms for error propagation can be used by the designer during refinement. They are controlled by a new exception--like mechanism. Furthermore, our approach aims to integrate functional verification as well as dependability verification with respect to given fault models.",
Organization = "In conjunction with 14th IEEE International Symposium on Object/Component/Service--oriented Real--time Distributed Computing",
isbn = "978-0-7695-4377-2",
doi = "10.1109/ISORCW.2011.27",
booktitle = "SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems",
Project = "COMPLEX"

}

@InProceedings{ Hartmann:2011:FGHCRMI1,

Author = "Philipp A. Hartmann and Philipp Ittershagen and Kim Gr{\"u}ttner and Frank Oppenheimer and Achim Rettberg",
Title = "A Framework for Generic HW/SW Communication using Remote Method Invocation",
Year = "2011",
Month = "03",
booktitle = "Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2011)",
Project = "COMPLEX"

}

@InProceedings{ ColasBigey:2011:ADVSSC,

Author = "Fabien Colas--Bigey and Sara Boccio and Chantal Ykman-Couvreur and Gianluca Palermo and Philipp A. Hartmann",
Title = "Audio Driven Video Surveillance System using COMPLEX design flow",
Year = "2011",
Month = "03",
booktitle = "Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2011)",
Project = "COMPLEX"

}

@InProceedings{ Gruettner:2011:ETPAVPHS,

Author = {Kim Gr{\"u}ttner and Kai Hylla and Sven Rosinger and Philipp A. Hartmann and Wolfgang Nebel},
Title = "Enabling Timing and Power Aware Virtual Prototyping of HW/SW Systems",
Year = "2011",
Month = "03",
abstract = "We propose the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SW systems. Our proposed flow combines system--level timing and power estimation techniques available in commercial tools with platform--based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C++ specification. These prototypes are enriched by static and dynamic power values as well as execution times. They allow a trade--off between different platforms, mapping alternatives, and optimization techniques, based on domainspecific workload scenarios.",
Organization = "In conjunction with Design, Automation, and Test in Europe Conference (DATE) 2011",
booktitle = "Workshop on Micro Power Management for Macro Systems on Chip (uPM2SoC)",
Project = "COMPLEX"

}

@InProceedings{ Ferrero:2011:UCDFSDA,

Author = {Francisco Ferrero and Kim Gr{\"u}ttner and Fernando Herrera and Gianluca Palermo and Bart Vanthournout and Emmanuel Vaumorin},
Title = "Using the COMPLEX Design Flow for Space Domain Applications",
Year = "2011",
Month = "03",
Organization = "In conjunction with Design, Automation, and Test in Europe Conference (DATE) 2011",
booktitle = "Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2011)",
Project = "COMPLEX"

}

@InProceedings{ Gruettner:2011:CEFTPARPHS,

Author = {Kim Gr{\"u}ttner},
Title = "The COMPLEX ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems ",
Year = "2011",
Month = "03",
abstract = "Consideration of an embedded systems timing behavior and power consumption at system--level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard and software as well as IP components. But prediction of the composed system behavior can hardly be made. In this session we present the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SW systems. Our proposed flow combines system--level timing and power estimation techniques available in commercial tools with platform--based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C++ specification. These prototypes are enriched by static and dynamic power values as well as execution times. They allow a trade--off between different platforms, mapping alternatives, and optimization techniques, based on domain--specific workload scenarios. The proposed flow will be implemented in the COMPLEX FP7 European integrated project (http://complex.offis.de).",
booktitle = "Design, Automation \& Test in Europe (DATE) 2011",
Project = "COMPLEX"

}

@InProceedings{ Hartmann:2011:CIPSS,

Author = "Philipp A. Hartmann",
Title = "sc{\_}vector{\&}lt;T{\&}gt; Container and the IEEE P1666--2011 SystemC Standard",
Year = "2011",
Month = "03",
abstract = " In many designs, a parametrisable number of modules, channels, ports, or other SystemC objects are used. Since such SystemC objects are usually named entities in the hierarchy, it is either required (in case of modules), or at least desired to pass a name parameter to the constructor of such objects. In this talk, an introduction to the convenience container called sc{\_}vector{\&}lt;T{\&}gt; for collections of such objects is given, which will is part of the upcoming IEEE P1666--2011 SystemC standard to lift this burden.",
booktitle = "23rd European SystemC User’s Group Meeting @ DATE 2011",
Project = "COMPLEX"

}

@InProceedings{ Ittershagen:2011:EgTHO,

Author = {Philipp Ittershagen and Philipp A. Hartmann and Kim Gr{\"u}ttner and Achim Rettberg},
Title = "Ein generisches Treiber--Framework zur HW/SW--Kommunikation mittels OSSS--RMI",
Year = "2011",
Month = "02",
abstract = {Die Realisierung der Kommunikation zwischen verschiedenen Tasks ist eine entscheidende Aufgabe bei der Entwicklung paralleler, eingebetteter Systeme. Wird im Laufe der Verfeinerung eines Systems die Zuordnung einzelner Komponenten auf unterschiedliche Berechnungseinheiten (Hardware, Software) ver{\"a}ndert, werden oftmals aufw{\"a}ndige Design{\"a}nderungen n{\"o}tig. In dieser Arbeit wird ein generisches Framework vorgestellt, um die Kommunikation von (Software--) Tasks mit sogenannten Shared Objects durchg{\"a}ngig zu erm{\"o}glichen. Die Kommunikation wird dabei {\"u}ber eine methodenbasierte Schnittstelle mit Hilfe des Remote Method Invocation (RMI) Protokolls realisiert. Die Objekte k{\"o}nnen dabei als dedizierte Hardware, in gemeinsam genutztem Speicher oder lokal zugreifbar vorliegen -- durch das hier vorgestellte Framework wird der Zugriff vereinheitlicht. Die Effektivit{\"a}t des Ansatzes wird anhand eines Beispiels evaluiert.},
booktitle = "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2011)",
Project = "COMPLEX",
      file = "mbmv2011-rmi4linux.pdf"

}

@InProceedings{ Kleen:2011:AUM,

Author = {Henning Kleen and Shangkun Xiao and Ralph G{\"o}rgen and Nico Bannow and Wolfgang Nebel},
Title = {Automatische {\"U}bersetzung von MATLAB/Simulink--Modellen nach SystemC--AMS},
Year = "2011",
Month = "02",
abstract = {Durch die wachsende Komplexit{\"a}t moderner eingebetteter Systeme und die zunehmende Integration analoger und digitaler Komponenten ergeben sich neue Herausforderungen bei der Verikation. Analoge und digitale Anteile m{\"u}ssen schon m{\"o}glichst fr{\"u}h im Entwurfsprozess gemeinsam betrachtet werden, weshalb M{\"o}glichkeiten zur komfortablen und schnellen Simulation von Mixed--Signal--Modellen unerl{\"a}sslich sind. In diesem Beitrag wird ein Werkzeug zur automatischen Generierung von SystemC--AMS--Modellen aus Simulink--Modellen vorgestellt. Es erm{\"o}glicht eine sehr einfache Kopplung analoger Systemteile, die in Simulink entworfen wurden, mit in SystemC beschriebenen digitalen Anteilen. Eine einfache API zum dynamischen Zugriff auf Modellparameter erm{\"o}glicht au{\ss}erdem die automatisierte Durchf{\"u}hrung von Testreihen mit wechselnden Parameterwerten. An zwei Beispielen aus dem Bereich der Automobilelektronik wird die {\"A}quivalenz der generierten SystemC--AMS Modelle zu denen in Simulink gezeigt und es wird ein Vergleich der Simulationsgeschwindigkeit durchgef{\"u}hrt.},
Organization = "ITG GMM GI",
booktitle = {14. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" MBMV 2011},
Project = "RapidMPSoC"

}

bib/2011.txt · Last modified: 2014-12-12 00:00 by Philipp Ittershagen