The increasing complexity of embedded HW/SW systems on one side and shortened product life cycles on the other, require support by the design methodology.
Hence, we develop in this application domain concepts and tools to improve the design process for so-called “Systems on a Chip” (SoC). It is the main approach to confront complexity with the enhancement of expressiveness of the electronic system level (ESL) languages, and thereby enable a seamless design process from a detailed specification all the way to the physical implementation. The modeling and refinement methodology enables the mapping of adaptive applications on diverse heterogeneous implementation platforms.
The Hardware/Software Design Methodology Group at OFFIS Institute for Information Technology works in the area of System-Level Design Methodology. In the past we have developed a design methodology (OSSS) and a tool (FOSSY) for system level synthesis of SystemC models.
The OSSS methodology defines a seamless design flow for embedded HW/SW systems. It enables the effective use of high-level SystemC and C++ features like classes (object-oriented design paradigm), templates and method based communication for the description of Software and Hardware. Furthermore, it supports the Accellera Systems Initiative Synthesis Subset for SystemC for low-level Hardware description and Hardware IP integration. With FOSSY we provided a tool for the automatic transformation of a system description in OSSS to an implementation.